ADIS16367BMLZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADIS16367BMLZ' PDF : 20 Pages View PDF
Data Sheet
ADIS16367
TIMING SPECIFICATIONS
TA = 25°C, VCC = 5 V, unless otherwise noted.
Table 2.
Normal Mode
Low Power Mode
(SMPL_PRD ≤ 0x09) (SMPL_PRD ≥ 0x0A)
Burst Read
Parameter Description
Min1 Typ Max Min1 Typ Max Min1 Typ Max Unit
fSCLK
Serial clock
0.01
2.0 0.01
0.3 0.01
1.0 MHz
tSTALL
Stall period between data
9
75
1/fSCLK
µs
tREADRATE
Read rate
40
100
µs
t
Chip select to clock edge
48.8
48.8
48.8
ns
CS
tDAV
tDSU
tDHD
tSCLKR, tSCLKF
tDR, tDF
E tSFS
t1
tx
T t2
t3
DOUT valid after SCLK edge
DIN setup time before SCLK rising edge
DIN hold time after SCLK rising edge
SCLK rise/fall times
DOUT rise/fall times
CS high after SCLK edge
Input sync positive pulse width
Input sync low time
Input sync to data-ready output
Input sync period
100
24.4
24.4
48.8
48.8
5
12.5
5
5
12.5
5
5
5
5
100
600
833
1 Guaranteed by design and characterization, but not tested in production.
100
24.4
48.8
12.5
5
12.5
5
5
5
100
600
833
E TIMING DIAGRAMS
CS
L SCLK
tCS
1
O DOUT
MSB
S DIN
R/W
2
3
4
5
6
tDAV
DB14
tDSU
DB13
DB12
tDHD
DB11
DB10
A6
A5
A4
A3
A2
15
16
tSFS
DB2
DB1
LSB
D2
D1
LSB
Figure 2. SPI Timing and Sequence
B tREADRATE
tSTALL
OCS
100
12.5
12.5
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
SCLK
Figure 3. Stall Time and Data Rate
SYNC
CLOCK (DIO4)
DATA
READY
t3
t2
t1
tX
Figure 4. Input Clock Timing Diagram
Rev. B | Page 5 of 20
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