ADJD-S311-CR999 View Datasheet(PDF) - Avago Technologies
Part Name
Description
MFG CO.
'ADJD-S311-CR999' PDF : 20 Pages View PDF
In the case of the master-receiver and slave-transmitter, the master generates a not acknowledge to signal the end of
the data transfer to the slave-transmitter. The master can then send a STOP or repeated START condition to begin a
new data transfer.
In all cases, the master generates the acknowledge or not acknowledge SCL clock pulse.
SDA
(SLAVE-TRANSMITTER)
SDA
(MASTER-RECEIVER)
SCL
(MASTER)
Figure 8. Master-Receiver Acknowledge
LSB
SDA left HIGH
by receiver
8
SDA left HIGH
by transmitter
Not
acknowledge
9
Acknowledge
clock pulse
P
Sr
STOP or repeated
START condition
Addressing
Each slave device on the serial bus needs to have a unique address. This is the first byte that is sent by the master-trans-
mitter after the START condition. The address is defined as the first seven bits of the first byte.
The eighth bit or least significant bit (LSB) determines the direction of data transfer. A ‘one’ in the LSB of the first byte
indicates that the master will read data from the addressed slave (master-receiver and slave-transmitter). A ‘zero’ in this
position indicates that the master will write data to the addressed slave (master-transmitter and slave-receiver).
A device whose address matches the address sent by the master will respond with an acknowledge for the first byte
and set itself up as a slave-transmitter or slave-receiver depending on the LSB of the first byte.
The slave address on ADJD-S311 is 0x74 (7-bits).
MSB
LSB
A6 A5 A4 A3 A2 A1 A0
R/W
1
1
1
0
1
0
0
Slave address
Figure 9. Slave Addressing
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