ADSP-2115BPZ-100 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-2115BPZ-100' PDF : 64 Pages View PDF
ADSP-21xx
TIMING PARAMETERS (ADSP-2103/2162/2164)
BUS REQUEST/GRANT
Parameter
10.24 MHz
Min Max
Frequency
Dependency
Min
Max
Unit
Timing Requirement:
tBH
BR Hold after CLKOUT High1
29.4
tBS
BR Setup before CLKOUT Low1
44.4
Switching Characteristic:
tSD
CLKOUT High to DMS, PMS, BMS, RD, WR Disable
44.4
tSDB DMS, PMS, BMS, RD, WR Disable to BG Low
0
tSE
BG High to DMS, PMS, BMS, RD, WR Enable
0
tSEC DMS, PMS, BMS, RD, WR Enable to CLKOUT High 14.4
0.25tCK + 5
ns
0.25tCK + 20
ns
0.25tCK + 20 ns
ns
ns
0.25tCK – 10
ns
NOTES
1If BR meets the tBS and tBH setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR
requires a pulse width greater than 10 ns.
Section 10.2.4, “Bus Request/Grant,” of the ADSP-2100 Family User’s Manual (1st Edition, ©1993) states that “When BR is recognized, the processor
responds immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the
cycle after BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
WR
BG
tSD
tSDB
tSEC
tSE
Figure 41. Bus Request/Grant
REV. B
–47–
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