ADSP-21160M View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21160M' PDF : 52 Pages View PDF
ADSP-21160M/ADSP-21160N
Link Ports—Receive, Transmit
For link ports, see Table 27, Table 28, Figure 24, and Figure 25.
Calculation of link receiver data setup and hold, relative to link
clock, is required to determine the maximum allowable skew
that can be introduced in the transmission path, between
LDATA and LCLK. Setup skew is the maximum delay that can
be introduced in LDATA, relative to LCLK (setup
skew = tLCLKTWH minimum – tDLDCH – tSLDCL). Hold skew is the
maximum delay that can be introduced in LCLK, relative to
LDATA (hold skew = tLCLKTWL minimum + tHLDCH – tHLDCL). Cal-
culations made directly from speed specifications result in
unrealistically small skew times, because they include multiple
tester guardbands.
Note that there is a two-cycle effect latency between the link
port enable instruction and the DSP enabling the link port.
Table 27. Link Ports—Receive
Parameter
Timing Requirements
tSLDCL
tHLDCL
tLCLKIW
tLCLKRWL
tLCLKRWH
Data Setup Before LCLK Low
Data Hold After LCLK Low1
LCLK Period
LCLK Width Low2
LCLK Width High3
Min
Max
Unit
2.5
ns
3
ns
tLCLK
ns
4
ns
4
ns
Switching Characteristics
tDLALC
LACK Low Delay After LCLK High4, 5
9
17
ns
1 For ADSP-21160M, specification is 2.5 ns, minimum.
2 For ADSP-21160M, specification is 6 ns, minimum.
3 For ADSP-21160M, specification is 6 ns, minimum.
4 LACK goes low with tDLALC relative to rise of LCLK after first nibble, but does not go low if the receiver’s link buffer is not about to fill.
5 For ADSP-21160M, specification is 12 ns, minimum.
LCLK
LDAT(7:0)
LACK (OUT)
RECEIVE
tLCLKRWH
tLCLKIW
tLCLKRWL
tSLDCL
IN
tHLDCL
tDLALC
Figure 24. Link Ports—Receive
Rev. C | Page 41 of 60 | February 2013
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