ADSP-21266 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21266' PDF : 44 Pages View PDF
ADSP-21266
Table 21. 16-Bit Memory Read Cycle
Parameter
Timing Requirements
tDRS
tDRH
Address/Data 15–0 Setup Before RD high
Address/Data 15–0 Hold After RD high
Switching Characteristics
tALEW
ALE Pulse Width
tALERW
ALE Deasserted to Read/Write Asserted
tADAS
Address/Data 15–0 Setup Before ALE Deasserted1
tADAH
Address/Data 15–0 Hold After ALE Deaserted1
tALEHZ
ALE Deasserted1 to Address/Data 15–0 In High Z
tRW
RD Pulse Width
D = (data cycle duration) × tCCLK
H = tCCLK (if a hold cycle is specified, else H = 0)
1 On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
Min
3.3
0
2 × tCCLK – 2
1 × tCCLK – 0.5
2.5 × tCCLK – 2.0
0.5 × tCCLK – 0.8
0.5 × tCCLK – 0.8
D–2
Max
Unit
ns
ns
ns
ns
ns
ns
ns
0.5tCCLK + 2.0
ns
ns
ALE
RD
WR
AD15-0
tALEW
tALERW
tADAS
tA D AH
VALID ADDRESS
tALEHZ
tRW
tDRS
tDRH
VALID DATA
Figure 18. 16-Bit Memory Read Cycle
Rev. B | Page 26 of 44 | May 2005
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