ADSP-21266 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21266' PDF : 44 Pages View PDF
ADSP-21266
Table 23. 16-Bit Memory Write Cycle
Parameter
Switching Characteristics
tALEW
tALERW
tADAS
tADAH
tWW
tALEHZ
ALE Pulse Width
ALE Deasserted to Read/Write Asserted
Address/Data 15–0 Setup Before ALE Deasserted1
Address/Data 15–0 Hold After ALE Deasserted1
WR Pulse Width
ALE Deasserted1 to Address/Data 15–0 In High Z
tDWS
Address/Data 15–0 Setup Before WR High
tDWH
Address/Data 15–0 Hold After WR High
D = (data cycle duration) × tCCLK
H = tCCLK (if a hold cycle is specified, else H = 0)
1 On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
Min
2 × tCCLK – 2
1 × tCCLK – 0.5
2.5 × tCCLK – 2.0
0.5 × tCCLK – 0.8
D–2
0.5 × tCCLK – 0.8
D
0.5 × tCCLK – 1.5 + H
Max
Unit
ns
ns
ns
ns
ns
0.5tCCLK + 2.0 ns
ns
ns
ALE
WR
RD
AD15-0
tALEW
tALERW
tADAS
tALEH
tADAH
VALID ADDRESS
tWW
tDWS
tDWH
VALID DATA
Figure 20. 16-Bit Memory Write Cycle
Rev. B | Page 28 of 44 | May 2005
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