ADSP-21266 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21266' PDF : 44 Pages View PDF
ADSP-21266
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the specifications in Table 24, Table 25,
Table 26, Table 27, Figure 21, and Figure 22 must be confirmed:
1) frame sync delay and frame sync setup and hold; 2) data delay
and data setup and hold; and 3) SCLK width.
Serial port signals (SCLK, FS, DxA,/DxB) are routed to the
DAI_P20–1 pins using the SRU. Therefore, the timing specifi-
cations provided below are valid at the DAI_P20–1 pins.
Table 24. Serial Ports—External Clock
Parameter
Min
Timing Requirements
tSFSE
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)1
2.5
tHFSE
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)1
2.5
tSDRE
Receive Data Setup Before Receive SCLK1
2.5
tHDRE
Receive Data Hold After SCLK1
2.5
tSCLKW
SCLK Width
7
tSCLK
SCLK Period
20
Max
Unit
ns
ns
ns
ns
ns
ns
Switching Characteristics
tDFSE
FS Delay After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)2
tHOFSE
FS Hold After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)2
2
tDDTE
Transmit Data Delay After Transmit SCLK2
tHDTE
Transmit Data Hold After Transmit SCLK2
2
1 Referenced to sample edge.
2 Referenced to drive edge.
7
ns
ns
7
ns
ns
Table 25. Serial Ports—Internal Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSI
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)1
6
ns
tHFSI
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)1
1.5
ns
tSDRI
Receive Data Setup Before SCLK1
tHDRI
Receive Data Hold After SCLK1
6
ns
1.5
ns
Switching Characteristics
tDFSI
tHOFSI
tDFSI
tHOFSI
tDDTI
tHDTI
FS Delay After SCLK (Internally Generated FS in Transmit Mode)2
FS Hold After SCLK (Internally Generated FS in Transmit Mode)2
FS Delay After SCLK (Internally Generated FS in Receive Mode)2
FS Hold After SCLK (Internally Generated FS in Receive Mode)2
Transmit Data Delay After SCLK2
Transmit Data Hold After SCLK2
tSCLKIW
Transmit or Receive SCLK Width
1 Referenced to the sample edge.
2 Referenced to drive edge.
3
ns
–1.0
ns
3
ns
–1.0
ns
3
ns
–1.0
ns
0.5tSCLK – 2
0.5tSCLK + 2
ns
Rev. B | Page 29 of 44 | May 2005
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