ADSP-21266 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21266' PDF : 44 Pages View PDF
ADSP-21266
DATA RECEIVE—INTERNAL CLOCK
DRIVE EDGE
tSCLKIW
SAMPLE EDGE
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
tHOFSI
tDFSI
DAI_P20–1
(DATA CHANNEL A/B)
tSFSI
tSDRI
tHFSI
tHDRI
DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE
tSCLKW
SAMPLE EDGE
DAI_P20–1
(SCLK)
tHOFSE
DAI_P20–1
(FS)
tDFSE
DAI_P20–1
(DATA CHANNEL A/B)
tSFSE
tSDRE
tHFSE
tHDRE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(DATA CHANNEL A/B)
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE
tSCLKIW
SAMPLE EDGE
tHOFSI
tDFSI
tSFSI
tHDTI
tDDTI
tHFSI
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE
SAMPLE EDGE
DAI_P20–1
(SCLK)
tHOFSE
DAI_P20–1
(FS)
tHDTE
DAI_P20–1
(DATA CHANNEL A/B)
tSCLKW
tDFSE
tSFSE
tDDTE
tHFSE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DAI_P20–1
SCLK (EXT)
DAI_P20–1
(DATA CHANNEL A/B)
DAI_P20–1
SCLK (INT)
DRIVE EDGE
tDDTEN
DRIVE EDGE
tDDTIN
DAI_P20–1
(DATA CHANNEL A/B)
Figure 22. Serial Ports
DRIVE EDGE
SCLK
tDDTTE
Rev. B | Page 31 of 44 | May 2005
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