ADSP-21365SBBC-ENG View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21365SBBC-ENG' PDF : 54 Pages View PDF
Preliminary Technical Data
Core Timer
The following timing specification applies to FLAG3 when it is
configured as the core timer (CTIMER).
Table 14. Core Timer
Parameter
Switching Characteristic
tWCTIM
CTIMER Pulse width
Min
4 × tPCLK – 1
Max
FLAG3
(CTIMER)
tW CT IM
Figure 11. Core Timer
Timer PWM_OUT Cycle Timing
The following timing specification applies to Timer0, Timer1,
and Timer2 in PWM_OUT (pulse width modulation) mode.
Timer signals are routed to the DAI_P20–1 pins through the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins.
Table 15. Timer PWM_OUT Timing
Parameter
Switching Characteristic
tPWMO
Timer Pulse Width Output
Min
2 tPCLK – 1
Max
2(231 – 1) tPCLK
DAI_P20-1
(TIMER2-0)
tP W MO
Figure 12. Timer PWM_OUT Timing
ADSP-21365/6
Unit
ns
Unit
ns
Rev. PrA | Page 21 of 54 | September 2004
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