ADSP-21367 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21367' PDF : 56 Pages View PDF
ADSP-21367/ADSP-21368/ADSP-21369
Input Data Port
The timing requirements for the IDP are given in Table 33. IDP
signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.
Table 33. IDP
Parameter
Min
Max
Unit
Timing Requirements
t1
SISFS
FS Setup Before SCLK Rising Edge
4
ns
t1
SIHFS
FS Hold After SCLK Rising Edge
2.5
ns
t1
SISD
SDATA Setup Before SCLK Rising Edge
2.5
ns
t1
SIHD
SDATA Hold After SCLK Rising Edge
2.5
ns
tIDPCLKW
Clock Width
9
ns
tIDPCLK
Clock Period
20
ns
1 DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(SDATA)
tIDPCLKW
SAMPLE EDGE
tIDPCLK
tSISFS
tSIHFS
tSISD
tSIHD
Figure 24. IDP Master Timing
Rev. C | Page 35 of 56 | January 2008
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