ADSP-21367 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21367' PDF : 56 Pages View PDF
ADSP-21367/ADSP-21368/ADSP-21369
JTAG Test Access Port and Emulation
Table 43. JTAG Test Access Port and Emulation
Parameter
Min
Timing Requirements
tTCK
TCK Period
tCK
tSTAP
TDI, TMS Setup Before TCK High
5
tHTAP
TDI, TMS Hold After TCK High
6
t1
SSYS
System Inputs Setup Before TCK High
7
t1
HSYS
System Inputs Hold After TCK High
18
tTRSTW
TRST Pulse Width
4tCK
Switching Characteristics
tDTDO
TDO Delay from TCK Low
t2
DSYS
System Outputs Delay After TCK Low
1 System Inputs = AD15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.
2 System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU.
Max
Unit
ns
ns
ns
ns
ns
ns
7
ns
tCK ÷ 2 + 7
ns
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
tTCK
tSTAP
tDTDO
tSSYS
tDSYS
tH TAP
tHSYS
Figure 36. IEEE 1149.1 JTAG Test Access Port
Rev. C | Page 45 of 56 | January 2008
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