ADSP-21369 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21369' PDF : 56 Pages View PDF
ADSP-21367/ADSP-21368/ADSP-21369
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 34. PDAP is the parallel mode operation of Channel 0 of
the IDP. For details on the operation of the IDP, see the IDP
chapter of the ADSP-21368 SHARC Processor Hardware
Reference. Note that the most significant 16 bits of external
PDAP data can be provided through the DATA31–16 pins. The
remaining four bits can only be sourced through DAI_P4–1.
The timing below is valid at the DATA31–16 pins.
Table 34. Parallel Data Acquisition Port (PDAP)
Parameter
Min
Max
Unit
Timing Requirements
t1
SPCLKEN
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge
2.5
ns
t1
HPCLKEN
PDAP_CLKEN Hold After PDAP_CLK Sample Edge
2.5
ns
t1
PDSD
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge
3.85
ns
t1
PDHD
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge
2.5
ns
tPDCLKW
Clock Width
7.0
ns
tPDCLK
Clock Period
20
ns
Switching Characteristics
tPDHLDD
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
2 × tPCLK + 3
ns
tPDSTRB
PDAP Strobe Pulse Width
2 × tPCLK – 1
ns
1 Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
DAI_P20-1
(PDAP_CLK)
DAI_P20-1
(PDAP_CLKEN)
DATA
SAMPLE EDGE
tPDCLKW
tPDCLK
tSPCLKEN
tPDSD
tHPCLKEN
tPDHD
DA I_P 20-1
(PDAP_STROBE)
tPDHLDD
Figure 25. PDAP Timing
tP D S T R B
Rev. C | Page 36 of 56 | January 2008
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