ADSP-21469 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469' PDF : 56 Pages View PDF
ADSP-21467/ADSP-21469
Table 10. Pin Descriptions (Continued)
Name
Type
State During/ After
Reset
Description
DDR2_ADDR15–0 O/T
High-Z/
driven low
DDR2 Address. DDR2 address pins.
DDR2_BA2-0
O/T
High-Z/
driven low
DDR2 Bank Address Input. Defines which internal bank an ACTIVATE, READ, WRITE,
or PRECHARGE command is being applied to. BA2–0define which mode registers,
including MR, EMR, EMR(2), and EMR(3) are loaded during the LOAD MODE REGISTER
command.
DDR2_CAS
O/T
High-Z/
driven high
DDR2 Column Address Strobe. Connect to DDR2_CAS pin; in conjunction with other
DDR2 command pins, defines the operation for the DDR2 to perform.
DDR2_CKE
O/T
High-Z/
driven low
DDR2 Clock Enable Output to DDR2. Active high signal. Connect to DDR2 CKE signal.
DDR2_CS3-0
O/T
High-Z/
driven high
DDR2 Chip Select. All commands are masked when DDR2_CS3-0 is driven high.
DDR2_CS3-0 are decoded memory address lines. Each DDR2_CS3-0 line selects the
corresponding external bank.
DDR2_DATA15-0 I/O/T
DDR2_DM1-0
O/T
High-Z
High-Z/
driven high
DDR2 Data In/Out. Connect to corresponding DDR2_DATA pins.
DDR2 Input Data Mask. Mask for the DDR2 write data if driven high. Sampled on both
edges of DDR2_DQS at DDR2 side. DM0 corresponds to DDR2_DATA 7–0 and DM1
corresponds to DDR2_DATA15–8.
DDR2_DQS1-0
DDR2_DQS1-0
I/O/T
High-Z
(Differential)
Data Strobe. Output with Write Data. Input with Read Data. DQS0 corresponds to
DDR2_DATA 7–0 and DQS1 corresponds to DDR2_DATA 15–8. Based on software
control via the DDR2CTL3 register, this pin can be single-ended or differential.
DDR2_RAS
O/T
High-Z/
driven high
DDR2 Row Address Strobe. Connect to DDR2_RAS pin; in conjunction with other
DDR2 command pins, defines the operation for the DDR2 to perform.
DDR2_WE
O/T
High-Z/
driven high
DDR2 Write Enable. Connect to DDR2_WE pin; in conjunction with other DDR2
command pins, defines the operation for the DDR2 to perform.
DDR2_CLK0,
DDR2_CLK0,
O/T
High-Z/
(Differential) driven low
DDR2 Memory Clocks. Two differential outputs available via software control
(DDR2CTL0 register). Free running, minimum frequency not guaranteed during reset.
DDR2_CLK1,
DDR2_CLK1
DDR2_ODT
O/T
High-Z/
driven low
DDR2 On Die Termination. ODT pin when driven high (along with other require-
ments) enables the DDR2 termination resistances. ODT is enabled/disabled regardless
of read or write commands.
The following symbols appear in the Type column of Table 10: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
O/D = open-drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels.
To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be
enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 k–
63 k. The range of an ipd resistor can be between 31 k–85 k. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at
typical conditions the voltage is in the range of 2.3 V to 2.7 V.
In this table, the DDR2 pins are SSTL18 compliant. All other pins are LVTTL compliant.
Rev. B | Page 15 of 76 | March 2013
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