ADSP-21477 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21477' PDF : 76 Pages View PDF
ADSP-21477/ADSP-21478/ADSP-21479
Timer WDTH_CAP Timing
The following timing specification applies to timer0 and timer1,
and in WDTH_CAP (pulse width count and capture) mode.
Timer signals are routed to the DPI_P14–1 pins through the
SRU. Therefore, the timing specification provided below is valid
at the DPI_P14–1 pins.
Table 26. Timer Width Capture Timing
Parameter
Timing Requirement
tPWI
Timer Pulse Width
Min
2 × tPCLK
Max
2 × (231 – 1) × tPCLK
Unit
ns
TIMER
CAPTURE
INPUTS
tPWI
Figure 14. Timer Width Capture Timing
Watchdog Timer Timing
Table 27. Watchdog Timer Timing
Parameter
Min
Max
Timing Requirement
tWDTCLKPER
Switching Characteristics
100
1000
tRST
WDT Clock Rising Edge to Watchdog Timer 3
7.6
RESET Falling Edge
tRSTPW
Reset Pulse Width
64 × tWDTCLKPER1
1 When the internal oscillator is used, the 1/tWDTCLKPER varies from 1.5 MHz to 2.5 MHz and the WDT_CLKIN pin should be pulled low.
Unit
ns
ns
ns
WDT_CLKIN
WDTRSTO
tWDTCLKPER
tRST
tRSTPW
Figure 15. Watchdog Timer Timing
Rev. C | Page 32 of 76 | July 2013
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