ADSP-21477 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21477' PDF : 76 Pages View PDF
ADSP-21477/ADSP-21478/ADSP-21479
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that
the precision clock generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG’s
inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All timing param-
eters and switching characteristics apply to external DAI pins
(DAI_P01 – DAI_P20).
Table 29. Precision Clock Generator (Direct Pin Routing)
Parameter
88-Lead LFCSP Package
All Other Packages
Min
Max
Min
Max
Unit
Timing Requirements
tPCGIP
tSTRIG
Input Clock Period
tPCLK × 4
PCG Trigger Setup Before 4.5
Falling Edge of PCG Input Clock
tPCLK × 4
ns
4.5
ns
tHTRIG
PCG Trigger Hold After Falling 3
Edge of PCG Input Clock
3
ns
Switching Characteristics
tDPCGIO
PCG Output Clock and Frame
Sync Active Edge Delay After 2.5
PCG Input Clock
2 × tPCLK
2.5
12.5
ns
tDTRIGCLK PCG Output Clock Delay After 2.5 + (2.5 × tPCGIP)
PCG Trigger
2 × tPCLK + (2.5 × tPCGIP) 2.5 + (2.5 × tPCGIP)
12.5 + (2.5 × tPCGIP) ns
tDTRIGFS PCG Frame Sync Delay After 2.5 + ((2.5 + D – PH) × 2 × tPCLK + ((2.5 + D – 2.5 + ((2.5 + D – PH) × 12.5 + ((2.5 + D – PH) ns
PCG Trigger
tPCGIP)
PH) × tPCGIP)
tPCGIP)
× tPCGIP)
tPCGOW1 Output Clock Period
2 × tPCGIP – 1
2 × tPCGIP – 1
ns
D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-214xx SHARC Processor Hardware Reference, “Precision Clock Generators”
chapter.
1 Normal mode of operation.
tSTRIG
DAI_Pn
DPI_Pn
PCG_TRIGx_I
tHTRIG
DAI_Pm
DPI_Pm
PCG_EXTx_I
(CLKIN)
DAI_Py
DPI_Py
PCK_CLKx_O
DAI_Pz
DPI_Pz
PCG_FSx_O
tDPCGIO
tDTRIGCLK
tDTRIGFS
tPCGIP
tDPCGIO
Figure 17. Precision Clock Generator (Direct Pin Routing)
tPCGOW
Rev. C | Page 34 of 76 | July 2013
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