ADSP-21477 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21477' PDF : 76 Pages View PDF
ADSP-21477/ADSP-21478/ADSP-21479
SDRAM Interface Timing
Table 31. SDRAM Interface Timing
133 MHz
150 MHz
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSSDAT
DATA Setup Before SDCLK
0.7
tHSDAT
DATA Hold After SDCLK
1.66
Switching Characteristics
tSDCLK1
SDCLK Period
7.5
tSDCLKH
SDCLK Width High
2.5
tSDCLKL
SDCLK Width Low
2.5
tDCAD2
Command, ADDR, Data Delay After SDCLK
5
tHCAD2
Command, ADDR, Data Hold After SDCLK
1
tDSDAT
Data Disable After SDCLK
6.2
tENSDAT
Data Enable After SDCLK
0.3
0.7
ns
1.5
ns
6.66
ns
2.2
ns
2.2
ns
4.75
ns
1
ns
5.3
ns
0.3
ns
1 Systems should use the SDRAM model with a speed grade higher than the desired SDRAM controller speed. For example, to run the SDRAM controller at 133 MHz the
SDRAM model with a speed grade of 143 MHz or above should be used. See Engineer-to-Engineer Note “Interfacing SDRAM memory to SHARC processors (EE-286)” for
more information on hardware design guidelines for the SDRAM interface.
2 Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDQM, SDCKE.
SDCLK
DATA (IN)
DATA (OUT)
COMMAND/ADDR
(OUT)
tSDCLK
tSDCLKH
tSSDAT
tHSDAT
tENSDAT
tSDCLKL
tDCAD
tHCAD
tDCAD
tHCAD
tDSDAT
Figure 19. SDRAM Interface Timing
Rev. C | Page 36 of 76 | July 2013
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