ADSP-21477 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21477' PDF : 76 Pages View PDF
ADSP-21477/ADSP-21478/ADSP-21479
AMI Read
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD,
AMI_WR, and strobe timing parameters only apply to asyn-
chronous access mode.
Table 32. AMI Read
Parameter
Min
Max
Unit
Timing Requirements
tDAD1, 2, 3
Address Selects Delay to Data Valid
tDRLD1, 3
AMI_RD Low to Data Valid
tSDS4, 5
Data Setup to AMI_RD High
2.6
tHDRH
Data Hold from AMI_RD High
0.4
tDAAK2, 6
AMI_ACK Delay from Address Selects
tDSAK4
AMI_ACK Delay from AMI_RD Low
Switching Characteristics
W + tSDCLK – 6.32
ns
W–3
ns
ns
ns
tSDCLK – 10 + W
ns
W – 7.0
ns
tDRHA
Address Selects Hold After AMI_RD High
RHC + 0.38
ns
tDARL2
Address Selects to AMI_RD Low
tSDCLK – 5
ns
tRW
AMI_RD Pulse Width
W – 1.4
ns
tRWR
AMI_RD High to AMI_RD Low
HI + tSDCLK – 1.2
ns
W = (number of wait states specified in AMICTLx register) × tSDCLK.
RHC = (number of Read Hold Cycles specified in AMICTLx register) × tSDCLK
Where PREDIS = 0
HI = RHC: Read to Read from same bank
HI = RHC + IC: Read to Read from different bank
HI = RHC + Max (IC, (4 × tSDCLK)) : Read to Write from same or different bank
Where PREDIS = 1
HI = RHC + Max (IC, (4 × tSDCLK)) : Read to Write from same or different bank
HI = RHC + (3 × tSDCLK): Read to Read from same bank
HI = RHC + Max (IC, (3 × tSDCLK)) : Read to Read from different bank
IC = (number of idle cycles specified in AMICTLx register) × tSDCLK
H = (number of hold cycles specified in AMICTLx register) × tSDCLK.
1 Data delay/setup: System must meet tDAD, tDRLD, or tSDS.
2 The falling edge of AMI_MSx, is referenced.
3 The maximum limit of timing requirement values for tDAD and tDRLD parameters are applicable for the case where AMI_ACK is always high and when the ACK feature is not used.
4 Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode.
5 Data hold: User must meet tHDRH in asynchronous access mode. See Test Conditions on Page 65 for the calculation of hold times given capacitive and dc loads.
6 AMI_ACK delay/setup: User must meet tdaak, or tdsak, for deassertion of AMI_ACK (low).
Rev. C | Page 37 of 76 | July 2013
Share Link: 
