ADSP-21477 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21477' PDF : 76 Pages View PDF
ADSP-21477/ADSP-21478/ADSP-21479
AMI Write
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD,
AMI_WR, and strobe timing parameters only apply to asyn-
chronous access mode.
Table 33. AMI Write
Parameter
Min
Max
Timing Requirements
tDAAK
AMI_ACK Delay from Address Selects1, 2
tDSAK
AMI_ACK Delay from AMI_WR Low1, 3
Switching Characteristics
tSDCLK – 10.1 + W
W – 7.1
tDAWH
Address Selects to AMI_WR Deasserted2
tSDCLK – 4.4 + W
tDAWL
Address Selects to AMI_WR Low2
tSDCLK – 4.5
tWW
AMI_WR Pulse Width
W – 1.3
tDDWH
Data Setup Before AMI_WR High
tSDCLK – 4.3 + W
tDWHA
Address Hold After AMI_WR Deasserted
H
tDWHD
Data Hold After AMI_WR Deasserted
H
tDATRWH
Data Disable After AMI_WR Deasserted4
tSDCLK – 1.37 + H
tWWR
AMI_WR High to AMI_WR Low5
tSDCLK – 1.5 + H
tDDWR
Data Disable Before AMI_RD Low
2 × tSDCLK – 7.1
tWDE
AMI_WR Low to Data Enabled
tSDCLK – 4.5
W = (number of wait states specified in AMICTLx register) × tSDCLK
H = (number of hold cycles specified in AMICTLx register) × tSDCLK
tSDCLK + 6.75 + H
1 AMI_ACK delay/setup: System must meet tDAAK, or tDSAK, for deassertion of AMI_ACK (low).
2 The falling edge of AMI_MSx is referenced.
3 Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode.
4 See Test Conditions on Page 65 for calculation of hold times given capacitive and dc loads.
5 For Write to Write: tSDCLK + H, for both same bank and different bank. For Write to Read: 3 × tSDCLK + H, for the same bank and different banks.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. C | Page 39 of 76 | July 2013
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