ADSP-21477 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21477' PDF : 76 Pages View PDF
ADSP-21477/ADSP-21478/ADSP-21479
Serial Ports
In slave transmitter mode and master receiver mode, the maxi-
mum serial port frequency is fPCLK/8. In master transmitter
mode and slave receiver mode, the maximum serial port clock
frequency is fPCLK/4.
To determine whether communication is possible between two
devices at clock speed, n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Table 34. Serial Ports—External Clock
Parameter
Timing Requirements
tSFSE1 Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in Either Transmit or
Receive Mode)
tHFSE1
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in Either Transmit or
Receive Mode)
tSDRE1 Receive Data Setup Before Receive SCLK
tHDRE1 Receive Data Hold After SCLK
tSCLKW SCLK Width
tSCLK SCLK Period
Switching Characteristics
tDFSE2
Frame Sync Delay After SCLK
(Internally Generated Frame Sync in Either Transmit or
Receive Mode)
tHOFSE2 Frame Sync Hold After SCLK
(Internally Generated Frame Sync in Either Transmit or
Receive Mode)
tDDTE2 Transmit Data Delay After Transmit SCLK
tHDTE2 Transmit Data Hold After Transmit SCLK
1 Referenced to sample edge.
2 Referenced to drive edge.
Serial port signals (SCLK, FS, Data Channel A, Data Channel B)
are routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P20–1 pins.
88-Lead LFCSP Package
All Other Packages
Min
Max
Min
Max
Unit
4
2.5
ns
4
2.5
ns
4
2.5
ns
4
2.5
ns
(tPCLK × 4) ÷ 2 – 1.5
(tPCLK × 4) ÷ 2 – 1.5
ns
tPCLK × 4
tPCLK × 4
ns
15
15
ns
2
2
ns
15
15
ns
2
2
ns
Rev. C | Page 41 of 76 | July 2013
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