ADSP-21990 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21990' PDF : 50 Pages View PDF
ADSP-21990
SPECIFICATIONS
Specifications subject to change without notice.
RECOMMENDED OPERATING CONDITIONS—ADSP-21990BBC
Parameter
Conditions
Min
Typ
Max
Unit
VDDINT
Internal (Core) Supply Voltage
2.375
2.5
2.625
V
VDDEXT
AVDD
External (I/O) Supply Voltage
Analog Supply Voltage
3.135
3.3
3.465
V
2.375
2.5
2.625
V
CCLK
DSP Instruction Rate, Core Clock
0
150
MHz
HCLK1, 2
Peripheral Clock Rate
0
75
MHz
CLKIN3
Input Clock Frequency
0
150
MHz
TJUNC4
TAMB
Silicon Junction Temperature
Ambient Operating Temperature
–40ºC
140ºC
ЊC
+85ºC
ЊC
1 The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be disabled.
2 The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLK ، 2, up to a maximum of a 75 MHz HCLK for the ADSP-21990BBC.
3 In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock generation PLL
circuit and the associated frequency ratio.
4 The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to ensure that
the power dissipation of the ADSP-21990 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not exceeded.
RECOMMENDED OPERATING CONDITIONS—ADSP-21990BST
Parameter
Conditions
Min
Typ
Max
Unit
VDDINT
VDDEXT
AVDD
Internal (Core) Supply Voltage
External (I/O) Supply Voltage
Analog Supply Voltage
2.375
2.5
2.625
V
3.135
3.3
3.465
V
2.375
2.5
2.625
V
CCLK
HCLK1, 2
CLKIN3
TJUNC4
TAMB
DSP Instruction Rate, Core Clock
Peripheral Clock Rate
Input Clock Frequency
Silicon Junction Temperature
Ambient Operating Temperature
0
0
0
–40ºC
160
MHz
80
MHz
160
MHz
140ºC
ЊC
+85ºC
ЊC
1 The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be disabled.
2 The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLK/2, up to a maximum of an 80 MHz HCLK for the ADSP-21990BST.
3 In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock generation PLL
circuit and the associated frequency ratio.
4 The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to ensure that
the power dissipation of the ADSP-21990 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not exceeded.
Rev. A | Page 19 of 50 | August 2007
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