ADSP-BF512 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF512' PDF : 68 Pages View PDF
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Parameter
Test Conditions
Min
Typical
Max
IDDINT10, 11
VDDINT Current
fCCLK> 0 MHz, fSCLK ≥ 0 MHz
IDDFLASH1
Flash Memory Supply Current 1
—Asynchronous Read
Table 13 +
(Table 14 × ASF) +
(0.20 × VDDINT × fSCLK)
10
6
IDDFLASH2
Flash Memory Supply Current 2
—Standby
4
12
IDDFLASH3
Flash Memory Supply Current 3
—Program and Erase
11
16
IDDOTP
VDDOTP Current
VDDOTP = 2.5 V, TJ = 25°C,
2
OTP Memory Read
IDDOTP
VDDOTP Current
VDDOTP = 2.5 V, TJ = 25°C,
2
OTP Memory Write
IPPOTP
VPPOTP Current
VPPOTP = 2.5 V, TJ = 25°C,
100
OTP Memory Read
IPPOTP
VPPOTP Current
VPPOTP = Table 19 V, TJ = 25°C,
3
OTP Memory Write
1 Applies to input balls.
2 Applies to JTAG input balls (TCK, TDI, TMS, TRST).
3 Applies to three-statable balls.
4 Applies to bidirectional balls SCL and SDA.
5 Applies to all signal balls, except SCL and SDA.
6 Guaranteed, but not tested.
7 See the ADSP-BF51x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.
8 Includes current on VDDEXT, VDDMEM, VDDOTP, and VPPOTP supplies. Clock inputs are tied high or low.
9 Guaranteed maximum specifications.
10Unit for VDDINT is V (Volts). Unit for fSCLK is MHz.
11See Table 12 for the list of IDDINT power vectors covered.
Unit
mA
mA
μA
mA
mA
mA
μA
mA
Total Power Dissipation
Total power dissipation has two components:
1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and pro-
cessor activity. Electrical Characteristics on Page 22 shows the
current dissipation for internal circuitry (VDDINT). IDDDEEPSLEEP
specifies static power dissipation as a function of voltage
(VDDINT) and temperature (see Table 13), and IDDINT specifies the
total power specification for the listed test conditions, including
the dynamic component as a function of voltage (VDDINT) and
frequency (Table 14).
There are two parts to the dynamic component. The first part is
due to transistor switching in the core clock (CCLK) domain.
This part is subject to an Activity Scaling Factor (ASF) which
represents application code running on the processor core and
L1 memories (Table 12).
The ASF is combined with the CCLK Frequency and VDDINT
dependent data in Table 14 to calculate this part. The second
part is due to transistor switching in the system clock (SCLK)
domain, which is included in the IDDINT specification equation.
Table 12. Activity Scaling Factors (ASF)1
IDDINT Power Vector
Activity Scaling Factor (ASF)
IDD-PEAK
1.29
IDD-HIGH
1.25
IDD-TYP
1.00
IDD-APP
0.85
IDD-NOP
0.70
IDD-IDLE
0.41
1 See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors
(EE-297). The power vector information also applies to the ADSP-BF51x
processors.
Rev. B | Page 23 of 68 | January 2011
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