ADSP-BF512 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF512' PDF : 68 Pages View PDF
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Parallel Peripheral Interface Timing
Table 30 and Figure 15 on Page 33, Figure 21 on Page 38, and
Figure 24 on Page 40 describe parallel peripheral interface
operations.
Table 30. Parallel Peripheral Interface Timing
VDDEXT
1.8 V Nominal
VDDEXT
2.5 V/3.3 V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tPCLKW
PPI_CLK Width
tSCLK – 1.5
tSCLK – 1.5
ns
tPCLK
PPI_CLK Period
2 × tSCLK – 1.5
2 × tSCLK – 1.5
ns
Timing Requirements - GP Input and Frame Capture Modes
tPSUD
External Frame Sync Startup Delay1
4 × tPCLK
4 × tPCLK
ns
tSFSPE
External Frame Sync Setup Before PPI_CLK
6.7
6.7
ns
(Nonsampling Edge for Rx, Sampling Edge for Tx)
tHFSPE
External Frame Sync Hold After PPI_CLK
1.75
1.75
ns
tSDRPE
Receive Data Setup Before PPI_CLK
4.1
3.5
ns
tHDRPE
Receive Data Hold After PPI_CLK
2
1.6
ns
Switching Characteristics - GP Output and Frame Capture Modes
tDFSPE
tHOFSPE
tDDTPE
tHDTPE
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
8
8
ns
1.7
1.7
ns
8.2
8
ns
2.3
1.9
ns
1 The PPI port is fully enabled 4 PPI clock cycles after the PAB write to the PPI port enable bit. Only after the PPI port is fully enabled are external frame syncs and data words
guaranteed to be received correctly by the PPI peripheral.
PPI_CLK
PPI_FS1/2
tPSUD
Figure 14. PPI with External Frame Sync Timing
PPI_CLK
PPI_FS1/2
PPI_DATA
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
tSFSPE
tHFSPE
tPCLKW
tPCLK
tSDRPE
tHDRPE
Figure 15. PPI GP Rx Mode with External Frame Sync Timing
Rev. B | Page 33 of 68 | January 2011
Share Link: 
