Preliminary Technical Data
ADSP-BF512/BF514/BF516/BF518 (F)
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
PPI_DATA
POLC = 0
PPI_CLK
PPI_CLK
POLC = 1
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
PPI_DATA
DATA
DRIVING/
FRAME
SYNC
SAMPLING
EDGE
DATA
DRIVING/
FRAME
SYNC
SAMPLING
EDGE
tSFSPE
tHFSPE
tHDTPE
tDDTPE
Figure 13. PPI GP Tx Mode with External Frame Sync Timing
FRAME
SYNC IS
DRIVEN
OUT
DATA0
IS
SAMPLED
tDFSPE
tHOFSPE
tSDRPE
tHDRPE
Figure 14. PPI GP Rx Mode with Internal Frame Sync Timing
Rev. PrE | Page 33 of 62 | March 2009