ADSP-BF522BBCZ-3A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF522BBCZ-3A' PDF : 88 Pages View PDF
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Clock Related Operating Conditions
for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors
Table 15 describes the core clock timing requirements for the
ADSP-BF523/ADSP-BF525/ADSP-BF527 processors. Take care
in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the
maximum core clock and system clock (see Table 17). Table 16
describes phase-locked loop operating conditions.
Use the nominal voltage setting (Table 15) for internal and
external regulators.
Table 15. Core Clock (CCLK) Requirements (All Instruction Rates1) for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors
Parameter
fCCLK
Core Clock Frequency (VDDINT =1.14 V minimum)
fCCLK
Core Clock Frequency (VDDINT =1.093 V minimum)
fCCLK
Core Clock Frequency (VDDINT = 1.045 V minimum)4
fCCLK
Core Clock Frequency (VDDINT = 0.95 V minimum)
1 See the Ordering Guide on Page 88.
2 Applies to 600 MHz models only. See the Ordering Guide on Page 88.
3 Applies to 533 MHz and 600 MHz models only. See the Ordering Guide on Page 88.
4 Applies only to automotive products. See Automotive Products on Page 87.
Nominal Voltage Setting Max
1.20 V
6002
1.15 V
5333
1.10 V
400
1.0 V
400
Unit
MHz
MHz
MHz
MHz
Table 16. Phase-Locked Loop Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors
Parameter
Min
fVCO
Voltage Controlled Oscillator (VCO) Frequency
60
(Commercial/Industrial Models)
fVCO
Voltage Controlled Oscillator (VCO) Frequency
70
(Automotive Models)
1 See the Ordering Guide on Page 88.
Max
Unit
Instruction Rate1
MHz
Instruction Rate1
MHz
Table 17. SCLK Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors
VDDEXT/VDDMEM
1.8 V Nominal1
VDDEXT/VDDMEM
2.5 V or 3.3 V Nominal
Parameter
Max
Max
fSCLK
CLKOUT/SCLK Frequency (VDDINT ≥ 1.14 V)2
100
fSCLK
CLKOUT/SCLK Frequency (VDDINT < 1.14 V)2
100
1333
100
1 If either VDDEXT or VDDMEM are operating at 1.8 V nominal, fSCLK is constrained to 100 MHz.
2 fSCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 38 on Page 47.
3 Rounded number. Actual test specification is SCLK period of 7.5 ns. See Table 38 on Page 47.
Unit
MHz
MHz
Rev. D | Page 31 of 88 | July 2013
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