ADSP-BF527 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF527' PDF : 80 Pages View PDF
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
TIMING SPECIFICATIONS
Specifications are subject to change without notice.
Clock and Reset Timing
Table 32 and Figure 9 describe clock and reset operations. Per
the CCLK and SCLK timing specifications in Table 12 to
Table 17, combinations of CLKIN and clock multipliers must
not select core/peripheral clocks in excess of the processor's
maximum instruction rate.
Table 32. Clock and Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
fCKIN
CLKIN Frequency (Commercial/ Industrial Models) 1,2, 3, 4 12
50
CLKIN Frequency (Automotive Models) 1, 2, 3, 4
14
50
tCKINL
tCKINH
tWRST
CLKIN Low Pulse1
CLKIN High Pulse1
RESET Asserted Pulse Width Low5
10
10
11 × tCKIN
Switching Characteristic
MHz
MHz
ns
ns
ns
tBUFDLAY
CLKIN to CLKBUF Delay
10
ns
1 Applies to PLL bypass mode and PLL nonbypass mode.
2 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 12 on Page 29 through
Table 14 on Page 29 and Table 15 on Page 31 through Table 17 on Page 31.
3 The tCKIN period (see Figure 9) equals 1/fCKIN.
4 If the DF bit in the PLL_CTL register is set, the minimum fCKIN specification is 24 MHz for commercial/industrial models and 28 MHz for automotive models.
5 Applies after power-up sequence is complete. See Table 33 and Figure 10 for power-up reset timing.
CLKIN
CLKBUF
tCKIN
tCKINL
tCKINH
RESET
tWRST
tBUFDLAY
tBUFDLAY
Figure 9. Clock and Reset Timing
Rev. D | Page 39 of 88 | July 2013
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