ADSP-BF527 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF527' PDF : 80 Pages View PDF
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Asynchronous Memory Write Cycle Timing
Table 35. Asynchronous Memory Write Cycle Timing
ADSP-BF522/ADSP-BF524/
ADSP-BF526
VDDMEM
1.8 V Nominal
VDDMEM
2.5 V or 3.3 V
Nominal
Parameter
Min Max Min
Max
Timing Requirements
tSARDY
ARDY Setup Before CLKOUT
4.0
4.0
tHARDY
ARDY Hold After CLKOUT
0.2
0.2
Switching Characteristics
tDDAT
DATA15–0 Disable After CLKOUT
6.0
6.0
tENDAT
DATA15–0 Enable After CLKOUT 0.0
0.0
tDO
Output Delay After CLKOUT1
6.0
6.0
tHO
Output Hold After CLKOUT1
0.8
0.8
1 Output balls include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AWE.
ADSP-BF523/ADSP-BF525/
ADSP-BF527
VDDMEM
1.8 V Nominal
VDDMEM
2.5 V or 3.3 V
Nominal
Min Max Min
Max
4.0
4.0
0.2
0.2
6.0
6.0
0.0
0.0
6.0
6.0
0.8
0.8
Unit
ns
ns
ns
ns
ns
ns
CLKOUT
AMSx
SETUP
2 CYCLES
PROGRAMMED
WRITE
ACCESS
2 CYCLES
ACCESS
EXTEND HOLD
1 CYCLE 1 CYCLE
tDO
tHO
ABE1–0
ADDR19–1
AWE
ARDY
DATA 15–0
tDO
tSARDY
tHARDY
tENDAT
tSARDY
tHO
tHARDY
tDDAT
Figure 12. Asynchronous Memory Write Cycle Timing
Rev. D | Page 42 of 88 | July 2013
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