ADSP-BF537BBCZ-5AV View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

ADSP-BF537BBCZ-5AV

Blackfin Embedded Processor

Analog Devices 

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ADSP-BF534/ADSP-BF536/ADSP-BF537

Table 10 through Table 12 describe the voltage/frequency

requirements for the ADSP-BF534/ADSP-BF536/ADSP-BF537

processor clocks. Take care in selecting MSEL, SSEL, and CSEL

ratios so as not to exceed the maximum core clock and system

clock. Table 13 describes phase-locked loop operating

conditions.

Table 10. Core Clock Requirements—500 MHz, 533 MHz, and 600 MHz Speed Grades1

Parameter

fCCLK Core Clock Frequency (VDDINT =1.30 V Minimum)2

fCCLK Core Clock Frequency (VDDINT = 1.20 V Minimum)3

fCCLK Core Clock Frequency (VDDINT =1.14 V Minimum)

fCCLK Core Clock Frequency (VDDINT =1.045 V Minimum)

fCCLK Core Clock Frequency (VDDINT = 0.95 V Minimum)

fCCLK Core Clock Frequency (VDDINT = 0.85 V Minimum)

fCCLK Core Clock Frequency (VDDINT = 0.8 V Minimum)

1 See Ordering Guide on Page 67.

2 Applies to 600 MHz models only. See Ordering Guide on Page 67.

3 Applies to 533 MHz and 600 MHz models only. See Ordering Guide on Page 67.

Internal Regulator Setting

1.30 V

1.25 V

1.20 V

1.10 V

1.00 V

0.90 V

0.85 V

Max

600

533

500

444

400

333

250

Unit

MHz

MHz

MHz

MHz

MHz

MHz

MHz

Table 11. Core Clock Requirements—400 MHz Speed Grade1

Parameter

Internal Regulator Setting

fCCLK Core Clock Frequency (VDDINT =1.14 V Minimum) 1.20 V

fCCLK Core Clock Frequency (VDDINT =1.045 V Minimum) 1.10 V

fCCLK Core Clock Frequency (VDDINT = 0.95 V Minimum) 1.00 V

fCCLK Core Clock Frequency (VDDINT = 0.85 V Minimum) 0.90 V

fCCLK Core Clock Frequency (VDDINT = 0.8 V Minimum) 0.85 V

1 See Ordering Guide on Page 67.

2 See Operating Conditions on Page 23.

120°C  TJ  105°C

Max

400

333

295

All2 Other TJ

Max

400

363

333

280

250

Unit

MHz

MHz

MHz

MHz

MHz

Table 12. Core Clock Requirements—300 MHz Speed Grade1

Parameter

fCCLK Core Clock Frequency (VDDINT = 1.14 V Minimum)

fCCLK Core Clock Frequency (VDDINT = 1.045 V Minimum)

fCCLK Core Clock Frequency (VDDINT = 0.95 V Minimum)

fCCLK Core Clock Frequency (VDDINT = 0.85 V Minimum)

fCCLK Core Clock Frequency (VDDINT = 0.8 V Minimum)

1 See Ordering Guide on Page 67.

Internal Regulator Setting

1.20 V

1.10 V

1.00 V

0.90 V

0.85 V

Max

300

255

210

180

160

Unit

MHz

MHz

MHz

MHz

MHz

Table 13. Phase-Locked Loop Operating Conditions

Parameter

fVCO

Voltage Controlled Oscillator (VCO) Frequency

Min

Max

50

Max fCCLK

Table 14. System Clock Requirements

Parameter

Condition

Max

fSCLK1

fSCLK1

VDDEXT 3.3 V or 2.5 V, VDDINT  1.14 V

VDDEXT 3.3 V or 2.5 V, VDDINT  1.14 V

1332

100

1 fSCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 27 on Page 34.

2 Rounded number. Actual test specification is SCLK period of 7.5 ns. See Table 27 on Page 34.

Unit

MHz

Unit

MHz

MHz

Rev. J | Page 24 of 68 | February 2014

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