ADSP-BF537BBCZ-5AV View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF537BBCZ-5AV' PDF : 68 Pages View PDF
ADSP-BF534/ADSP-BF536/ADSP-BF537
300 MHz/400 MHz1
500 MHz/533 MHz/600 MHz2
Parameter
Test Conditions
Min
Typ Max
Min
Typ Max
Unit
CIN
Input
fIN = 1 MHz,
Capacitance13, 14 TAMBIENT = 25°C,
VIN = 2.5 V
IDD-IDLE
VDDINT Current in VDDINT = 1.0 V,
Idle
fCCLK = 50 MHz,
TJ = 25°C, ASF = 0.43
IDD-TYP
VDDINT Current
VDDINT = 1.14 V,
fCCLK = 300 MHz,
TJ = 25°C, ASF = 1.00
IDD-TYP
IDDDEEPSLEEP15
VDDINT Current
VDDINT = 1.14 V,
fCCLK = 400 MHz,
TJ = 25°C, ASF = 1.00
VDDINT Current in VDDINT = 1.0 V,
Deep Sleep
fCCLK = 0 MHz,
Mode
TJ = 25°C, ASF = 0.00
IDDSLEEP
VDDINT Current in VDDINT = 1.0 V,
Sleep Mode
fSCLK = 25 MHz,
TJ = 25°C
IDD-TYP
VDDINT Current
VDDINT = 1.20 V,
fCCLK = 533 MHz,
TJ = 25°C, ASF = 1.00
IDD-TYP
VDDINT Current VDDINT = 1.30 V,
fCCLK = 600 MHz,
TJ = 25°C, ASF = 1.00
IDDHIBERNATE15, 16 VDDEXT Current in VDDEXT = 3.60 V,
Hibernate State CLKIN=0 MHz,
TJ = maximum, with
voltage regulator off
(VDDINT = 0 V)
IDDRTC
IDDDEEPSLEEP15
VDDRTC Current VDDRTC = 3.3 V, TJ= 25°C
VDDINT Current in fCCLK = 0 MHz,
Deep Sleep
fSCLK =0 MHz
Mode
IDDSLEEP15, 17
IDDINT18
VDDINT Current in fCCLK = 0 MHz,
Sleep Mode
fSCLK 0 MHz
VDDINT Current
fCCLK 0 MHz,
fSCLK 0 MHz
8
14
100
125
6
9.5
50 100
8
pF
24
mA
113
mA
138
mA
16
mA
19.5
mA
185
mA
227
mA
50 100
A
20
Table 16
IDDDEEPSLEEP + (0.14
× VDDINT × fSCLK)
IDDSLEEP +
(Table 18 × ASF)
20
A
Table 15
mA
IDDDEEPSLEEP + (0.14 mA
× VDDINT × fSCLK)
IDDSLEEP +
mA
(Table 18 × ASF)
1 Applies to all 300 MHz and 400 MHz speed grade models. See Ordering Guide on Page 67.
2 Applies to all 500 MHz, 533 MHz, and 600 MHz speed grade models. See Ordering Guide on Page 67.
3 Applies to all output and bidirectional pins except port F pins, port G pins, and port H pins.
4 Applies to port F pins PF7–0.
5 Applies to port F pins PF15–8, all port G pins, and all port H pins.
6 Maximum combined current for Port F7–0.
7 Maximum total current for all port F, port G, and port H pins.
8 Applies to all input pins except PJ4.
9 Applies to input pin PJ4 only.
10Applies to JTAG input pins (TCK, TDI, TMS, TRST).
11Applies to three-statable pins.
12Applies to bidirectional pins PJ2 and PJ3.
13Applies to all signal pins.
14Guaranteed, but not tested.
15See the ADSP-BF537 Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.
16CLKIN must be tied to VDDEXT or GND during hibernate.
17In the equations, the fSCLK parameter is the system clock in MHz.
18See Table 17 for the list of IDDINT power vectors covered.
Rev. J | Page 26 of 68 | February 2014
Share Link: 
