ADSP-BF538 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF538' PDF : 56 Pages View PDF
Preliminary Technical Data
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ΔV
to be the difference between the ADSP-BF538/ADSP-BF538F
processor’s output voltage and the input threshold for the
device requiring the hold time. CL is the total bus capacitance
(per data line), and IL is the total leakage or three-state current
(per data line). The hold time will be tDECAY plus the various out-
put disable times as specified in the Timing Specifications on
Page 24 (for example tDSDAT for an SDRAM write cycle as shown
in Table 20 on Page 29).
tDIS
VOH
(MEASURED)
VOL
(MEASURED)
REFERENCE
SIGNAL
tDIS_MEASURED
tENA
VOH (MEASURED) ؊ ⌬V
VOL (MEASURED) + ⌬V
tDECAY
tENA-MEASURED
VOH
2.0V (MEASURED)
1.0V
VOL
(MEASURED)
tTRIP
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS
VOLTAGE TO BE APPROXIMATELY 1.5V.
Figure 41. Output Enable/Disable
TO
OUTPUT
PIN
50⍀
30pF
1.5V
Figure 42. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
ADSP-BF538/ADSP-BF538F
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 42). VLOAD is 1.5 V for VDDEXT
(nominal) = 2.5/3.3 V. Figure 43 through Figure 52 on Page 49
show how output rise time varies with capacitance. The delay
and hold specifications given should be derated by a factor
derived from these figures. The graphs in these figures may not
be linear outside the ranges shown.
14 ABE0 (133 MHz DRIVER), VDDEXT (MIN) = 2.25V, TEMPERATURE = 85°C
12
RISE TIME
10
FALL TIME
8
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 43. Typical Output Delay or Hold for Driver A at VDDEXT MIN
ABE0 (133 MHz DRIVER), VDDEXT (MAX) = 3.65V, TEMPERATURE = 85°C
12
10
RISE TIME
8
FALL TIME
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 44. Typical Output Delay or Hold for Driver A at VDDEXT MAX
Rev. PrD | Page 47 of 56 | May 2006
Share Link: 
