ADSP-BF538F View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF538F' PDF : 60 Pages View PDF
ADSP-BF538/ADSP-BF538F
POWER DISSIPATION
Total power dissipation has two components: one due to inter-
nal circuitry (PINT) and one due to the switching of external
output drivers (PEXT). Table 33 through Table 35 show the power
dissipation for internal circuitry (VDDINT).
See the ADSP-BF53x Blackfin Processor Hardware Reference
Manual for definitions of the various operating -modes and for
instructions on how to minimize system power.
Many operating conditions can affect power dissipation. System
designers should refer to EE-TBD: Estimating Power for
ADSP-BF538/ADSP-BF538F Blackfin Processors.” This docu-
ment will provide detailed information for optimizing your
design for lowest power.
Table 33. Internal Power Dissipation (Hibernate mode)
I2
DDHIBERNATE
I3
DDRTC
IDD (nominal1)
TBD
TBD
Unit
μA
μA
1 Nominal assumes an operating temperature of 25°C.
2 Measured at VDDEXT = 3.65 V with voltage regulator off (VDDINT = 0 V).
3 Measured at VDDRTC = 3.3 V at 25°C.
Table 34. Internal Power Dissipation (Deep Sleep mode)
V1
DDINT
0.80
IDD (nominal2)
19.00
0.90
25.00
1.00
32.00
1.10
40.00
1.26
54.00
1 Assumes VDDINT is regulated externally.
2 Nominal assumes an operating temperature of 25°C.
Unit
mA
mA
mA
mA
mA
Table 35. Internal Power Dissipation (Full On1 mode)
V2
DDINT
@
fCCLK
(MHz)
0.8 @ 50 MHz
0.8 @ 250 MHz
0.9 @ 300 MHz
1.0 @ 350 MHz
1.1 @ 444 MHz
1.26 @ 500 MHz
IDD (nominal3)
32.00
Unit
mA
72.00
mA
98.00
mA
132.00
mA
180.00
mA
235.00
mA
1 Processor executing 75% dual MAC, 25% ADD with moderate data bus
activity.
2 Assumes VDDINT is regulated externally.
3 Nominal assumes an operating temperature of 25°C.
Preliminary Technical Data
TEST CONDITIONS
All timing parameters appearing in this data sheet were mea-
sured under the conditions described in this section. Figure 40
shows the measurement point for AC measurements (except
output enable/disable). The measurement point VMEAS is 1.5 V
for VDDEXT (nominal) = 2.5/3.3 V.
INPUT
OR 1.5V
OUTPUT
1.5V
Figure 40. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
Output Enable Time Measurement
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving.
The output enable time tENA is the interval from the point when a
reference signal reaches a high or low voltage level to the point
when the output starts driving as shown on the right side of Fig-
ure 41, “Output Enable/Disable,” on page 47.
The time tENA_MEASURED is the interval, from when the reference
signal switches, to when the output voltage reaches VTRIP(high)
or VTRIP(low). VTRIP(high) is 2.0 V and VTRIP(low) is 1.0 V for
VDDEXT (nominal) = 2.5/3.3 V. Time tTRIP is the interval from
when the output starts driving to when the output reaches the
VTRIP(high) or VTRIP(low) trip voltage.
Time tENA is calculated as shown in the equation:
tENA = tENA_MEASURED – tTRIP
If multiple pins (such as the data bus) are enabled, the measure-
ment value is that of the first pin to start driving.
Output Disable Time Measurement
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time tDIS is the
difference between tDIS_MEASURED and tDECAY as shown on the left
side of Figure 41.
tDIS = tDIS_MEASURED – tDECAY
The time for the voltage on the bus to decay by ΔV is dependent
on the capacitive load CL and the load current IL. This decay time
can be approximated by the equation:
tDECAY = (CLΔV) ⁄ IL
The time tDECAY is calculated with test loads CL and IL, and with
ΔV equal to 0.5 V for VDDEXT (nominal) = 2.5/3.3 V.
The time tDIS+_MEASURED is the interval from when the reference sig-
nal switches, to when the output voltage decays ΔV from the
measured output high or output low voltage.
Rev. PrD | Page 46 of 56 | May 2006
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