ADSP-BF538F View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF538F' PDF : 56 Pages View PDF
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Serial Peripheral Interface Port—Master Timing
Table 28 and Figure 25 describe SPI port master operations.
Table 28. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
tSSPIDM
Data Input Valid to SCK Edge (Data Input Setup)
tHSPIDM
SCK Sampling Edge to Data Input Invalid
Switching Characteristics
tSDSCIM
tSPICHM
tSPICLM
tSPICLK
tHDSM
tSPITDM
tDDSPIDM
tHDSPIDM
SPI0SELx Low to First SCK edge (x=0 or 1)
Serial Clock High period
Serial Clock Low period
Serial Clock Period
Last SCK Edge to SPI0SELx High (x=0 or 1)
Sequential Transfer Delay
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
Min
Max
7.5
–1.5
2tSCLK –1.5
2tSCLK – 1.5
2tSCLK – 1.5
4tSCLK – 1.5
2tSCLK – 1.5
2tSCLK – 1.5
0
6
–1.0
4.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPISELx
(OUTPUT)
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
tSDSCIM
tSPICHM
tSPICLM
tSPICLM
tSPICHM
tDDSPIDM
MOSI
(OUTPUT)
MSB
CPHA=1
MISO
(INPUT)
tSSPIDM
tHSPIDM
MSB VALID
tDDSPIDM
MOSI
(OUTPUT)
MSB
CPHA=0
MISO
(INPUT)
tSSPIDM
tHSPIDM
MSB VALID
tSPICLK
tHDSM
tSPITD M
tHDSPIDM
LSB
tSSPIDM
tHSPIDM
LSB VALID
tHDSPIDM
LSB
LSB VALID
Figure 25. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. PrD | Page 39 of 56 | May 2006
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