ADSP-BF539 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF539' PDF : 68 Pages View PDF
ADSP-BF539/ADSP-BF539F
Preliminary Technical Data
ELECTRICAL CHARACTERISTICS
Parameter1
Test Conditions
Min
VOH
High Level Output Voltage2
@ VDDEXT = +3.0 V, IOH = –0.5 mA
2.4
VOL
Low Level Output Voltage2
@ VDDEXT = 3.0 V, IOL = 2.0 mA
IIH
High Level Input Current3
@ VDDEXT = Maximum, VIN = VDD Maximum
IIHP
High Level Input Current JTAG4 @ VDDEXT = Maximum, VIN = VDD Maximum
IIL
Low Level Input Current3
@ VDDEXT = Maximum, VIN = 0 V
IOZH
Three-State Leakage Current5
@ VDDEXT = Maximum, VIN = VDD Maximum
IOZL
Three-State Leakage Current5
@ VDDEXT = Maximum, VIN = 0 V
CIN
Input Capacitance6, 7
fCCLK = 1 MHz, TAMBIENT = 25°C, VIN = 2.5 V
IDDHIBERNATE
I8
DDDEEPSLEEP
VDDINT Current in Hibernate State VDDEXT = 3.65 V with voltage regulator off (VDDINT = 0 V)
VDDINT Current in Deep Sleep Mode VDDINT = 0.95 V, TJUNCTION = 25°C
IDDSLEEP
I 8, 9
DD_TYP
I 8, 9
DD_TYP
VDDINT Current in Sleep Mode
VDDINT Current Dissipation (Typical)
VDDINT Current Dissipation (Typical)
VDDINT = 0.95 V, TJUNCTION = 25°C @ fSCLK = 50 MHz
VDDINT = 0.95 V, fCCLK = 50 MHz, TJUNCTION = 25°C
VDDINT = 1.14 V, fCCLK = 400 MHz, TJUNCTION = 25°C
VDDINT = 1.2 V, fCCLK = 500 MHz, TJUNCTION = 25°C
IDDRTC
VDDRTC Current
VDDRTC = 3.3 V, TJUNCTION = 25°C
1 Specifications subject to change without notice.
2 Applies to output and bi-directional pins.
3 Applies to input pins except JTAG inputs.
4 Applies to JTAG input pins (TCK, TDI, TMS, TRST).
5 Applies to three-statable pins.
6 Applies to all signal pins.
7 Guaranteed, but not tested.
8 See Power Dissipation on Page 57.
9 Processor executing 75% dual MAC, 25% ADD with moderate data bus activity.
Typical
4
50
28
32
47
181
227
20
Max Unit
V
0.4 V
10.0 μA
50.0 μA
10.0 μA
10.0 μA
10.0 μA
8
pF
μA
mA
mA
mA
mA
mA
μA
Rev. PrF | Page 28 of 68 | September 2006
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