ADSP-BF539 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF539' PDF : 68 Pages View PDF
Preliminary Technical Data
Asynchronous Memory Write Cycle Timing
Table 19 and Table 20 on Page 35 and Figure 14 and Figure 15
on Page 36 describe asynchronous memory write cycle opera-
tions for synchronous and for asynchronous ARDY.
Table 19. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
Parameter
Timing Requirements
tSARDY
ARDY Setup Before the Falling Edge of CLKOUT
tHARDY
ARDY Hold After the Falling Edge of CLKOUT
Switching Characteristics
tDDAT
tENDAT
tDO
tHO
DATA15–0 Disable After CLKOUT
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT1
Output Hold After CLKOUT1
1 Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
Table 20. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
Parameter
Timing Requirements
tDANR
ARDY Negated Delay from AMSx Asserted1
tHAA
ARDY Asserted Hold After ARE Negated
Switching Characteristics
tDDAT
tENDAT
tDO
tHO
DATA15–0 Disable After CLKOUT
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT2
Output Hold After CLKOUT2
1 S = number of programmed setup cycles, WA = number of programmed write access cycles.
2 Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
ADSP-BF539/ADSP-BF539F
Min
Max
Unit
4.0
ns
0.0
ns
6.0
ns
1.0
ns
6.0
ns
0.8
ns
Min
Max
Unit
(S+WA–2)*tSCLK ns
0.0
ns
6.0
ns
1.0
ns
6.0
ns
0.8
ns
Rev. PrF | Page 35 of 68 | September 2006
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