ADSP-BF539 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF539' PDF : 68 Pages View PDF
ADSP-BF539/ADSP-BF539F
Preliminary Technical Data
Serial Peripheral Interface (SPI) Ports
—Master Timing
Table 29 and Figure 26 describe SPI ports master operations.
Table 29. Serial Peripheral Interface (SPI) Ports—Master Timing
Parameter
Timing Requirements
tSSPIDM
Data Input Valid to SCK Edge (Data Input Setup)
tHSPIDM
SCK Sampling Edge to Data Input Invalid
Switching Characteristics
tSDSCIM
tSPICHM
tSPICLM
tSPICLK
tHDSM
tSPITDM
tDDSPIDM
tHDSPIDM
SPIxSELy Low to First SCK edge
Serial Clock High period
Serial Clock Low period
Serial Clock Period
Last SCK Edge to SPIxSELy High
Sequential Transfer Delay
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
Min
Max
7.5
–1.5
2tSCLK –1.5
2tSCLK – 1.5
2tSCLK – 1.5
4tSCLK – 1.5
2tSCLK – 1.5
2tSCLK – 1.5
0
6
–1.0
4.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPIxSELy
(OUTPUT)
SCKx
(CPOL = 0)
(OUTPUT)
SCKx
(CPOL = 1)
(OUTPUT)
tSDSCIM
tSPICHM
tSPICLM
tSPICLM
tSPICHM
tDDSPIDM
MOSIx
(OUTPUT)
MSB
CPHA=1
MISOx
(INPUT)
tSSPIDM
tHSPIDM
MSB VALID
tDDSPIDM
MOSIx
(OUTPUT)
MSB
CPHA=0
MISOx
(INPUT)
tSSPIDM
tHSPIDM
MSB VALID
tSPICLK
tHDSM
tSPITD M
tHDSPIDM
LSB
tSSPIDM
tHSPIDM
LSB VALID
tHDSPIDM
LSB
LSB VALID
Figure 26. Serial Peripheral Interface (SPI) Ports—Master Timing
Rev. PrF | Page 48 of 68 | September 2006
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