ADSP-BF539 View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

ADSP-BF539

Blackfin® Embedded Processor

Analog Devices 

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ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

Timer Cycle Timing

Table 32 and Figure 30 describe timer expired operations. The

input signal is asynchronous in “width capture mode” and

“external clock mode” and has an absolute maximum input fre-

quency of fSCLK/2 MHz.

Table 32. Timer Cycle Timing

Parameter

Minimum Maximum Unit

Timing Characteristics

tWL

Timer Pulsewidth Input Low1 (measured in SCLK cycles)

tWH

Timer Pulsewidth Input High1 (measured in SCLK cycles)

Switching Characteristic

1

SCLK

1

SCLK

tHTO

Timer Pulsewidth Output2 (measured in SCLK cycles)

1

(232–1)

SCLK

1 The minimum pulsewidths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.

2 The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232–1) cycles.

CLKOUT

TMRx

(PWM OUTPUT MODE)

tHTO

TMRx

(WIDTH CAPTURE AND

EXTERNAL CLOCK MODES)

tWL

tWH

Figure 30. Timer PWM_OUT Cycle Timing

Rev. PrF | Page 52 of 68 | September 2006

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