ADSP-BF539F View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF539F' PDF : 60 Pages View PDF
ADSP-BF539/ADSP-BF539F
Preliminary Technical Data
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in power dissipation, while reducing
the voltage by 25% reduces power dissipation by more than
40%. Further, these power savings are additive, in that if the
clock frequency and supply voltage are both reduced, the power
savings can be dramatic.
The Dynamic Power Management feature of the ADSP-
BF539/ADSP-BF539F processor allows both the processor’s
input voltage (VDDINT) and clock frequency (fCCLK) to be dynam-
ically controlled.
The savings in power dissipation can be modeled using the
Power Savings Factor and % Power Savings calculations.
The Power Savings Factor is calculated as:
Power Savings Factor
=
-f--C---C---L--K---R--E---D--
fCCLKNOM
×
⎛
⎝
V-V----D-D--D-D--I-IN-N--T-T--N-R--OE---DM--⎠⎞
2
×
⎛
⎝
-T----R---E--D--
TNOM
⎞
⎠
where the variables in the equations are:
• fCCLKNOM is the nominal core clock frequency
• fCCLKRED is the reduced core clock frequency
• VDDINTNOM is the nominal internal supply voltage
• VDDINTRED is the reduced internal supply voltage
• TNOM is the duration running at fCCLKNOM
• TRED is the duration running at fCCLKRED
The Power Savings Factor is calculated as:
% Power Savings = (1 – Power Savings Factor) × 100%
VOLTAGE REGULATION
The Blackfin processor provides an on-chip voltage regulator
that can generate processor core voltage levels
1.0 V(–5%/+10%) to 1.2V(–5% / +10%) from an external
2.7 V to 3.6 V supply. Figure 6 shows the typical external com-
ponents required to complete the power management system.†
The regulator controls the internal logic voltage levels and is
programmable with the Voltage Regulator Control Register
(VR_CTL) in increments of 50 mV. To reduce standby power
consumption, the internal voltage regulator can be programmed
to remove power to the processor core while I/O power
(VDDRTC, MXEVDD, VDDEXT) is still supplied. While in the
hibernate state, I/O power is still being applied, eliminating the
need for external buffers. The voltage regulator can be activated
from this power-down state either through an RTC wakeup, a
CAN wakeup, an MXVR wakeup, or by asserting RESET, which
will then initiate a boot sequence. The regulator can also be dis-
abled and bypassed at the user’s discretion.
† See EE-228: Switching Regulator Design Considerations for ADSP-BF533
Blackfin Processors.
I/O
POWER
PINS
INTERNAL
POWER
PINS
100 µF
100 µF 1 µF
10 µH
0.1 µF
ZHCS1000
2.7 V - 3.6 V
INPUT VOLTAGE
RANGE
FDS9431A
VROUT1-0
EXTERNAL COMPONENTS
NOTE: VROUT1-0 SHOULD BE TIED TOGETHER EXTERNALLY
AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A.
Figure 6. Voltage Regulator Circuit
CLOCK SIGNALS
The ADSP-BF539/ADSP-BF539F processor can be clocked by
an external crystal, a sine wave input, or a buffered, shaped
clock derived from an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the ADSP-BF539/ADSP-BF539F proces-
sor includes an on-chip oscillator circuit, an external crystal
may be used. The crystal should be connected across the CLKIN
and XTAL pins, with two capacitors connected as shown in
Figure 7. Capacitor values are dependent on crystal type and
should be specified by the crystal manufacturer. A parallel-reso-
nant, fundamental frequency, microprocessor-grade crystal
should be used.
CLKIN
XTAL
BLACKFIN
PROCESSOR
CLKOUT
Figure 7. External Crystal Connections
As shown in Figure 8 on Page 17, the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a user programmable 0.5× to 64× multipli-
cation factor (bounded by specified minimum and maximum
VCO frequencies). The default multiplier is 10×, but it can be
modified by a software instruction sequence. On-the-fly fre-
quency changes can be effected by simply writing to the
PLL_DIV register.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
Rev. PrF | Page 16 of 68 | September 2006
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