ADSP-BF539F View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF539F' PDF : 68 Pages View PDF
ADSP-BF539/ADSP-BF539F
Preliminary Technical Data
External Port Bus Request and Grant Cycle Timing
Table 22 and Table 23 on Page 38 and Figure 17 and Figure 18
on Page 40 describe external port bus request and grant cycle
operations for synchronous and for asynchronous BR.
Table 22. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Parameter
Timing Requirements
tBS
BR Setup to Falling Edge of CLKOUT
tBH
Falling Edge of CLKOUT to BR Deasserted Hold Time
Switching Characteristics
tSD
CLKOUT Low to xMS, Address, and RD/WR disable
tSE
CLKOUT Low to xMS, Address, and RD/WR enable
tDBG
CLKOUT High to BG High Setup
tEBG
CLKOUT High to BG Deasserted Hold Time
tDBH
CLKOUT High to BGH High Setup
tEBH
CLKOUT High to BGH Deasserted Hold Time
Table 23. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
Parameter
Timing Requirements
tWBR
BR Pulsewidth
Switching Characteristics
tSD
CLKOUT Low to xMS, Address, and RD/WR disable
tSE
CLKOUT Low to xMS, Address, and RD/WR enable
tDBG
CLKOUT High to BG High Setup
tEBG
CLKOUT High to BG Deasserted Hold Time
tDBH
CLKOUT High to BGH High Setup
tEBH
CLKOUT High to BGH Deasserted Hold Time
Min
Max
Unit
4.0
ns
0.0
ns
4.5
ns
4.5
ns
3.6
ns
3.6
ns
3.6
ns
3.6
ns
Min
2 x tSCLK
Max
4.5
4.5
3.6
3.6
3.6
3.6
Unit
ns
ns
ns
ns
ns
ns
ns
Rev. PrF | Page 38 of 68 | September 2006
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