ADSP-BF539WBBCZ-5A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF539WBBCZ-5A' PDF : 68 Pages View PDF
Preliminary Technical Data
“FINE” ADJUSTMENT
REQUIRES PLL SEQUENCING
“COARSE” ADJUSTMENT
ON-THE-FLY
CLKI N
PLL
0.5´ -64´
VCO
Ă· 1, 2, 4, 8
Ă· 1:15
CCLK
SCLK
SCLK ÂŁ CCLK
SCLK ÂŁ 133MHz
Figure 8. Frequency Modification Methods
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 7 illustrates typical system clock ratios:
Table 7. Example System Clock Ratios
Signal Name Divider Ratio Example Frequency Ratios (MHz)
SSEL3–0
VCO/SCLK VCO
SCLK
0001
1:1
100
100
0110
6:1
300
50
1010
10:1
500
50
The maximum frequency of the system clock is fSCLK. Note that
the divisor ratio must be chosen to limit the system clock fre-
quency to its maximum of fSCLK. The SSEL value can be changed
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
Note that when the SSEL value is changed, it will affect all the
peripherals that derive their clock signals from the SCLK signal.
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 8. This programmable core clock capability is useful for
fast core frequency modifications.
Table 8. Core Clock Ratios
Signal Name
CSEL1–0
00
01
10
11
Divider Ratio
VCO/CCLK
1:1
2:1
4:1
8:1
Example Frequency Ratios
VCO
CCLK
300
300
300
150
500
125
200
25
ADSP-BF539/ADSP-BF539F
BOOTING MODES
The ADSP-BF539/ADSP-BF539F processor has three mecha-
nisms (listed in Table 9) for automatically loading internal L1
instruction memory after a reset. A fourth mode is provided to
execute from external memory, bypassing the boot sequence.
Table 9. Booting Modes
BMODE1–0 Description
00
Execute from 16-bit external memory
(bypass boot ROM)
01
Boot from 8-bit or 16-bit flash or Boot from on-chip
flash (ADSP-BF539F only)
10
Boot from SPI serial master connected to SPI0
11
Boot from SPI serial slave EEPROM /flash
(8-,16-, or 24-bit address range, or Atmel
AT45DB041, AT45DB081, or AT45DB161serial flash)
connected to SPI0
The BMODE pins of the Reset Configuration Register, sampled
during power-on resets and software initiated resets, implement
the following modes:
• Execute from 16-bit external memory – Execution starts
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
• Boot from 8-bit external flash memory – The 8-bit flash
boot routine located in boot ROM memory space is set up
using asynchronous memory bank 0. For ADSP-BF539F
processors, if FCE is connected to AMS0, then the on-chip
flash is booted. All configuration settings are set for the
slowest device possible (3-cycle hold time; 15-cycle R/W
access times; 4-cycle setup).
• Boot from SPI serial EEPROM/flash (8-, 16-, or 24-bit
addressable, or Atmel AT45DB041, AT45DB081, or
AT45DB161) connected to SPI0– The SPI0 port uses the
PF2 output pin to select a single SPI EEPROM/flash device,
submits a read command and successive address bytes
(0x00) until a valid 8-, 16-, or 24-bit, or Atmel addressable
device is detected, and begins clocking data into the begin-
ning of the L1 instruction memory.
• Boot from SPI host device connected to SPI0 – The Black-
fin processor operates in SPI slave mode and is configured
to receive the bytes of the .LDR file from an SPI host (mas-
ter) agent. To hold off the host device from transmitting
while the boot ROM is busy, the Blackfin processor asserts
a GPIO pin, called host wait (HWAIT), to signal the host
device not to send any more bytes until the flag is deas-
serted. The flag is chosen by the user and this information
is transferred to the Blackfin processor via bits 10:5 of the
FLAG header in the .LDR image.
For each of the boot modes, a 10-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Rev. PrF | Page 17 of 68 | September 2006
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