ADUC7033BSTZ-88 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADUC7033BSTZ-88' PDF : 140 Pages View PDF
ADuC7033
Table 3. SPI Master Mode Timing (PHASE Mode = 0)
Parameter Description
tSL
SCLK low pulse width1
tSH
SCLK high pulse width1
tDAV
Data output valid after SCLK edge2
tDOSU
Data output setup before SCLK edge
tDSU
Data input setup time before SCLK edge
tDHD
Data input hold time after SCLK edge2
tDF
Data output fall time
tDR
Data output rise time
tSR
SCLK rise time
tSF
SCLK fall time
Min
Typ
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
0
3 × tUCLK
½ tSL
3.5
3.5
3.5
3.5
1 tHCLK depends on the clock divider (CD) bits in POWCON MMR. tHCLK = tUCLK/2CD.
2 tUCLK = 48.8 ns and corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
Max
(2 × tUCLK) + (2 × tHCLK)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
MOSI
MISO
tSH
tSL
tDOSU
tDAV
tDF
MSB
tDR
BITS [6:1]
tSR
tSF
LSB
MSB IN
BITS [6:1]
LSB IN
tDSU tDHD
Figure 3. SPI Master Mode Timing (PHASE Mode = 0)
Rev. B | Page 11 of 140
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