Signal Processor for Single-Chip CCD B/W Camera
1 EIA for 1/60 s accumulation; CCIR for 1/50 s accumulation
Ai2410
O: Can be used
3. VD/HC sync (external sync) mode
VD input with normal cycle
VD input with longer cycle than
Interlace
normal interlace
Field readout
Frame readout
Field readout
Frame readout
XSUB pulse OFF 1
O
O
O
X
Serial input electronic
O
O
X
X
shutter ON
Parallel input
O
O
X
X
electronic shutter ON
Auto iris ON
O
O
X
X
1 EIA for 1/60 s accumulation; CCIR for 1/50 s accumulation
O: Can be used
X: Cannot be used
Note Only in the VD/HD sync mode, the external synchronization is possible during which VD pulses with longer cycle than
normal are input to the VR/SYNC pin
18
Preliminary