ASAHI KASEI
[AK4516A]
SYSTEM DESIGN
Figure 13 shows the system connection example. An evaluation board [AKD4516A] is available which
demonstrates the optimum layout, power supply arrangement and measurement results.
Figure 13 . Typical Connection Diagram
NOTE:
- LRCK=fs, SCLK ≥ 32fs or 64fs, MCLK=256fs or 384fs
- Power supply lines of VA and VD should be distributed separately from the point with low
impedance of regulator or connecting to the resistor of 10 ohms.
- When LOUT(ROUT) drives some capacitive load, some resistor should be added in series
between LOUT(ROUT) and capacitive load.
- The capacitor value on VCOM depends on low frequency noise level of power supply.
M0026-E-00
- 35 -
1998/08