ALTAIR04-900 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ALTAIR04-900' PDF : 29 Pages View PDF
Application information
ALTAIR04-900
divider. Its resistance ratio as well as the individual resistance values have to be properly
chosen (see “Section 5.4: Constant voltage operation” and “Section 5.6: Voltage feed-
forward block”).
The maximum IZCD/FB sunk/sourced current must not exceed ±2 mA (AMR) in all Vin range
conditions. No capacitor is allowed between ZCD pin and the auxiliary transformer.
The switching frequency is 166 kHz top-limited, as the converter operating frequency can
increase excessively at light load and on high input voltage.
A starter block is also used to start up the system, that is, to turn on the MOSFET during the
converter power-up, when any or a very small signal is available on ZCD pin.
The starter frequency is 2 kHz if COMP pin is below burst-mode threshold, 1 V, while it
becomes 8 kHz if this voltage exceeds this value.
After the first few cycles initiated by the starter, as the voltage developed across the auxiliary
winding arms the ZCD circuit, MOSFET turn-on starts to be locked to transformer
demagnetization, hence setting up QR operation.
The starter is also active when the IC is in CC regulation and the output voltage is not so
high to allow the ZCD triggering.
If the demagnetization completes, hence a negative-going edge appears on ZCD pin, after a
time exceeding TBLANK time, the MOSFET turns on again, with some delay to assure
minimum voltage at turn-on. If, instead, the negative-going edge appears before TBLANK has
elapsed, it is ignored and the first negative-going edge after TBLANK turns on the MOSFET.
Therefore one or more drain ringing cycles are skipped (“valley-skipping-mode”, Figure 12)
and the switching frequency cannot exceed 1/TBLANK.
Figure 12. Drain ringing cycle skipping as the load is progressively reduced
VDS
VDS
VDS
TON
TFW
TV
Tosc
Pin = Pin'
( limit condition)
t
t
t
Tosc
Tosc
Pin = Pin'' < Pin'
Pin = Pin''' < Pin''
When the system operates in valley-skipping-mode, uneven switching cycles may be
observed under some line/load conditions, due to the fact that the off-time of the MOSFET
changes with discrete steps of one ringing cycle, while the off-time needed for cycle-by-
cycle energy balance may fall in between. Thus one or more longer switching cycles are
compensated by one or more shorter cycles and vice versa. However, this mechanism is
absolutely normal and there is no appreciable impact on the performance of the converter or
on its output voltage.
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DocID18211 Rev 3
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