PRELIMINARY
AC CHARACTERISTICS
Addresses
CE#
OE#
WE#
DQ7
tRC
VA
tACC
tCE
tCH
tOEH
tOE
tDF
tOH
Complement
VA
Complement True
DQ0–DQ6
Status Data
Status Data True
VA
Valid Data
Valid Data
High Z
High Z
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
20818C-16
Figure 13. Data# Polling Timings (During Embedded Algorithms)
Addresses
CE#
OE#
WE#
DQ6/DQ2
tRC
VA
tACC
tCE
tCH
tOE
tOEH
tDF
High Z
tOH
Valid Status
(first read)
VA
Valid Status
(second read)
VA
VA
Valid Status
(stops toggling)
Valid Data
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
20818C-17
Figure 14. Toggle Bit Timings (During Embedded Algorithms)
29
Am29F002/Am29F002N