PRELIMINARY
TEST CONDITIONS
5.0
Device
Under
Test
CL
6.2 kΩ
2.7 kΩ
Note:
Diodes are IN3064 or equivalents.
Figure 8. Test Setup
20637B-13
Table 6. Test Specifications
Test Condition
All
-55
others Unit
Output Load
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
30
100
pF
Input Rise and Fall Times
5
20
ns
Input Pulse Levels
0.0–3.0 0.45–2.4 V
Input timing measurement
reference levels
1.5 0.8, 2.0 V
Output timing measurement
reference levels
1.5 0.8, 2.0 V
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
Steady
OUTPUTS
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
KS000010-PAL
24
Am29F200A