AM85C30-8PC View Datasheet(PDF) - Advanced Micro Devices
Part Name
Description
MFG CO.
'AM85C30-8PC' PDF : 68 Pages View PDF
Auto RTS Reset
On the CMOS ESCC, if bit D0 of WR15 and bit D2 of
WR7′ are set to 1 and the channel is in SDLC mode, the
RTS pin may be reset early in the Tx Underrun routine
and the RTS pin will remain active until the last 0 bit of
the closing flag leaves the TxD pin as shown in Figure
16. Note that in order for this to function properly, bits D3
and D2 of WR10 must be set to 1 and 0, respectively.
CRC Character Reception
NMOS Am8530H
On the NMOS Am8530H, when the end-of-frame flag is
detected, the contents of the Receive Shift Register are
transferred to the Receive Data FIFO regardless of the
number of bits accumulated. Because of the 3-bit delay
between the Receive SYNC Register and Receive Shift
AMD
Register, the last 2 bits of the CRC check character
received are never transferred to the Receive Data
FIFO. Thus, the received CRC characters are unavail-
able for use.
CMOS Am85C30
On the Am85C30, the option of being able to receive the
complete CRC characters generated by the transmitter
is provided when both bit D0 of WR15 and bit D5 of WR7′
are set to 1. When these 2 bits are set and an end-of-
frame flag is detected, the last 2 bits of the CRC will
be clocked into the Receive Shift Register before its
contents are transferred to the Receive Data FIFO. The
data-CRC boundary and CRC character bit formats for
each Residue Code provided are shown in Figures 17A
through 17D for each character length selected.
Data Being Sent
Data
CRC
CRC
Flag
Tx Underrun/EOM
RTS Bit D1 WR5
RTS Pin (Active Low)
Figure 16. Auto RTS Reset Mode
10216F-20
Am85C30
31
Share Link: 
