APW7066 View Datasheet(PDF) - Anpec Electronics
Part Name
Description
MFG CO.
'APW7066' PDF : 35 Pages View PDF
APW7066
Function Description
Operational Modes
The APW7066 has two independent synchronous buck
converters, and it also has DDR mode operation to allow
VOUT2 to track VOUT1.
In independent mode operation, connect a capacitor from
each SS/EN pin to the ground to set each regulator’s soft-
start time. The 3.3V reference VREF can be used directly,
or divided by two resistors for REFIN, since the VREF is
controlled by the SS2/EN2.
DDR mode is chosen by connecting the SS2/EN2 pin to
VCC(5V). In this mode, SS2/EN2 function will be disabled,
SS1/EN1 is used to control soft start and enable both
VOUT1 and VOUT2. The VOUT1 is used as the REFIN for
the VOUT2, that makes VOUT2 to track VOUT1.
VREF
REFIN
SS1/EN1
SS2/EN2
SS3/EN3
GND
Phase Shift
The APW7066 has phase shift function, use the REFOUT
pin to select the phase shift between Independent mode
and DDR mode. Connect the REFOUT to VCC to get the 0
degre in either mode. In this case, the buffer of the
REFOUT is disabled. Leave the REFOUT open shifts the
phase 90 degrees in DDR mode, or 180 degrees in Inde-
pendent mode, REFOUT can be used in this case (see
Table 1.).
Table1. Mode and Phase Selection
MODE
SS2/EN2 REFOUT REFIN
PHASE
SHIFT
CH1/CH2
DDR
DDR
VCC
VCC
VCC VOUT1 0 deg SS1/EN1
for CH1
Open VOUT1 90 deg and CH2
Independent SS2 cap VCC
Independent SS2 cap Open
VREF
VREF
0 deg
180 deg
SS1/EN1
for CH1
SS2/EN2
for CH2
The advantage of Phase shift is to avoid overlapping the
switching current spikes of the two channels, or interac-
tion between the channels; it also reduces the RMS cur-
rent of the input capacitors, allowing fewer caps to be
employed. However, the phase shift between the rising
edge of LGATE1 and LGATE2 (See figure 3.), depending
on the duty cycles, the falling edges of the two channels
might overlap; so the user should check it.
Figure 1. Independent Mode Circuit
VOUT1
VCC
REFIN
SS1/EN1
SS2/EN2
SS3/EN3
GND
Figure 2.DDR Mode Circuit
Copyright © ANPEC Electronics Corp.
Rev. A.8 - Aug., 2009
LG1
LG2
(0deg)
LG2
(90deg)
LG2
(180deg)
0
90
180
0
Figure 3. Phase of LG2 with respect to rising edge of LG1
21
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