AS5SS256K36DQ-7.5/XT View Datasheet(PDF) - Micross Components
Part Name
Description
MFG CO.
'AS5SS256K36DQ-7.5/XT' PDF : 17 Pages View PDF
SSRAM
AS5SS256K36
CLK
ADSP\
ADSC\
ADDRESS
BWE\
BWa\ - BWd\
GW\
CE\
(See Note)
ADV\
OE\
tKC WRITE TIMING
tKL
tADSS
tADSH
tKH
tADSS
tAS
A1
tAH
tADSH
A2
BYTE WRITE signals are
ignored when ADSP\ is LOW.
tCES
t WS
(Note 5) t WH
ADSC\ extends burst.
tADSS
tADSH
A3
t WS
t WH
tCEH
(Note 3)
tDS tDH
(Note 4)
t AAS
ADV\ suspends burst.
tAAH
D
High-Z
D(A1)
tOEHZ
Q
D(A2) D(A2+1)
(Note 1)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1) D(A3+2)
Single WRITE
BURST READ
BURST WRITE
Don’t Care
Undefined
Extended BURST WRITE
NOTE:
1. D(A2) refers to output from address A2. D(A2+1) refers to output from the next internal burst address following A2.
2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW.
3. OE\ must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period prior to the byte write enable
inputs being sampled.
4. ADV\ must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW\ LOW; or GW\ HIGH and BEW\, BWa\ - BWd\ LOW.
AS5SS256K36
Rev. 4.4 10/13
13
Micross Components reserves the right to change products or specifications without notice.
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