Austin Semiconductor, Inc.
FLASH
AS8F512K32
Data Polling Timings (During Embedded Algorithms)
Addresses
CE\
tRC
VA
11111222221113333311222244444231111133355555322222444411114333334444455555
VA
1111122222333331111144444222225555533333111116666644222224441111333334444455555
VA
tACC
tCE
tCH
tOE
OE\
tOEH
tDF
WE\
tOH
DQ7
Complement
Complement True
Valid Data
High-Z
DQ0-DQ6
Status Data
Status Data True
Valid Data
High-Z
NOTE: VA=Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
Toggle Bit Timings ( During Embedded Algorithms)
Addresses
CE\
OE\
WE\
tRC
VA
tACC
tCE
tCH
tOE
tOEH
DQ6/DQ2
11111222223333311111111114444422222222225555533333444445555566666
tDF
tOH
Valid Status
(first read)
VA
111112222233333444445555566666
VA
Valid Status
Valid Status
VA
Valid Status
NOTE: VA=Valid address; not required for DQ6. Illustration shows first two status cycles after command sequence, last
status read cycle, and array data read cycle.
AS8F512K32
Rev. 5.2 09/07
15
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