Figure 6-5. Bus Timing
SCL
tSU.STA
tF
tLOW
tHD.STA
tHIGH
tHD.DAT
tLOW
tSU.DAT
SDA In
SDA Out
tAA
tDH
tR
tSU.STO
tBUF
Figure 6-6. Write Cycle Timing
SCL
SDA
8th Bit
ACK
WORDN
Stop
Condition
(1)
tWR
Start
Condition
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of
the internal clear/write cycle.
8
AT24C128C [DATASHEET]
Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015