AT24C16D-PHM View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT24C16D-PHM' PDF : 27 Pages View PDF
8.5 Power-Up Requirements and Reset Behavior
During a power-up sequence, the VCC supplied to the AT24C16D should monotonically rise from GND to the
minimum VCC level as specified in Section 8.2 with a slew rate no greater than 1V/μs.
8.5.1
Device Reset
To prevent inadvertent write operations or any other spurious events from occurring during a power-up
sequence, the AT24C16D includes a Power-On-Reset (POR) circuit. Upon power-up, the device will not
respond to any commands until the VCC level crosses the internal voltage threshold (VPOR) that brings the device
out of reset and into standby mode.
The system designer must ensure the instructions are not sent to the device until the VCC supply has reached a
stable value greater than or equal to the minimum VCC level. Additionally, once the VCC is greater than or equal
to the minimum VCC level, the bus Master must wait at least tPUP before sending the first command to the device.
See Table 8-4 for the values associated with these power-up parameters.
Table 8-4. Power-up Conditions(1)
Symbol Parameter
Min
Max Units
tPUP
Time required after VCC is stable before the device can accept commands.
100
μs
VPOR
Power-On Reset Threshold Voltage.
1.5
V
tPOFF
Minimum time at VCC = 0V between power cycles.
1
ms
Note: 1. These parameters are characterized but they are not 100% tested in production.
If an event occurs in the system where the VCC level supplied to the AT24C16D drops below the maximum VPOR
level specified, it is recommended that a full power cycle sequence be performed by first driving the VCC pin to
GND, waiting at least the minimum tPOFF time, and then performing a new power-up sequence in compliance
with the requirements defined in this section.
8.6 Pin Capacitance
Table 8-5. Pin Capacitance(1)
Symbol Test Condition
Max
CI/O
Input/Output Capacitance (SDA)
8
CIN
Input Capacitance (SCL)
6
Note: 1. This parameter is characterized but is not 100% tested in production.
Units
pF
pF
Conditions
VI/O = 0V
VIN = 0V
8.7 EEPROM Cell Performance Characteristics
Table 8-6. EEPROM Cell Performance Characteristics
Operation
Write Endurance(1)
Data Retention(2)
Test Condition
TA = 25°C, VCC(min)< VCC < VCC(max)
Byte or Page Write Mode
TA = 55°C, VCC(min)< VCC < VCC(max)
Min
1,000,000
100
Max
Units
—
Write Cycles
—
Years
Notes: 1. Write endurance performance is determined through characterization and the qualification process.
2. The data retention capability is determined through qualification and is checked on each device in production.
AT24C16D [DATASHEET] 15
Atmel-8906C-SEEPROM-AT24C16D-Datasheet_052015
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